Digital Logic (DL) IOE Syllabus

Marks Distribution

Chapters	Hours	Marks
Introduction	3	6
Digital Logic	1	4
Combinational Logic Circuits	5	8
Data Processing Circuits	5	10
Arithmetic Circuits	5	8
Flip Flops	5	8
Registers	2	4
Counters	5	8
Sequential Machines	8	12
Digital Integrate Circuits	4	8
Applications	2	4
Total	45	80

Here is Digital Logic IOE Syllabus!

1. Introduction

1.1. Definitions for Digital Signals

1.2. Digital Waveforms

1.3. Digital Logic

1.4. Moving and Storing Digital Information

1.5. Digital Operations

1.6. Digital Computer

1.7. Digital Integrated Circuits

1.8. Digital IC Signal Levels

1.9. Clock wave form

1.10. Coding

1.10.1. ASCII Code

1.10.2. BCD

1.10.3. The Excess – 3 Code

1.10.4. The Gray Code

2. Digital Logic

2.1. The Basic Gates – NOT, OR, AND

2.2. Universal Logic Gates – NOR, NAND

2.3. AND‐OR‐INVERT Gates

2.4. Positive and Negative Logic

2.5. Introduction to HDL

3. Combinational Logic Circuits

3.1. Boolean Laws and Theorems

3.2. Sum‐of‐Products Method

3.3. Truth Table to Karnaugh Map

3.4. Pairs, Quads, and Octets

3.5. Karnaugh Simplifications

3.6. Don’t Care Conditions

3.7. Product‐of‐Sums Method

3.8. Product‐of‐Sums Simplification

3.9. Hazards and Hazard Covers

3.10. HDL Implementation Models

4. Data Processing Circuits

4.1. Multiplexetures

4.2. Demultiplexetures

4.3. Decoder

4.4. BCD‐to‐Decimal Decoders

4.5. Seven‐Segment Decoders

4.6. Encoder

4.7. Exclusive‐OR Gates

4.8. Parity Generators and Checkers

4.9. Magnitude Comparator

4.10. Read‐Only Memory

4.11. Programmable Array Logic

4.12. Programmable Logic Arrays

4.13. Troubleshooting with a Logic Probe

4.14. HDL Implementation of Data Processing Circuits

5. Arithmetic Circuits

5.1. Binary Addition

5.2. Binary Subtraction

5.3. Unsigned Binary Numbers

5.4. Sign‐Magnitude Numbers

5.5. 2’s Complement Representation

5.6. 2’s Complement Arithmetic

5.7. Arithmetic Building Blocks

5.8. The Adder‐Subtracter

5.9. Fast Adder

5.10. Arithmetic Logic Unit

5.11. Binary Multiplication and Division

5.12. Arithmetic Circuits Using HDL

6. Flip Flops

6.1. RS Flip‐Flops

6.2. Gated Flip‐Flops

6.3. Edge‐Triggered RS Flip‐Flops

6.4. Egde Triggered D Flip‐Flops

6.5. Egde Triggered J K Flip‐Flops

6.6. Flip‐Flop Timing

6.7. J K Mater‐ Slave Flip‐Flops

6.8. Switch Contacts Bounds Circuits

6.9. Varius Representation of Flip‐Flops

6.10. Analysis of Sequencial Circuits

7. Registers

7.1. Types of Registers

7.2. Serial In – Serial Out

7.3. Serial In – Parallel Out

7.4. Parallel In – Serial Out

7.5. Parallel In – Parallel Out

7.6. Applications of Shift Registers

8. Counters

8.1. Asynchronous Counters

8.2. Decoding Gates

8.3. Synchronous Counters

8.4. Changing the Counter Modulus

8.5. Decade Counters

8.6. Presettable Counters

8.7. Counter Design as a Synthesis Problem

8.8. A Digital Clock

9. Sequential Machines

9.1. Synchronous machines

9.1.1. Clock driven models and state diagrams

9.1.2. Transition tables, Redundant states

9.1.3. Binary assignment

9.1.4. Use of flip‐flops in realizing the models

9.2. Asynchronous machines

9.2.1. Hazards in asynchronous system and use of redundant branch

9.2.2. Allowable transitions

9.2.3. Flow tables and merger diagrams

9.2.4. Excitation maps and realization of the models

10. Digital Integrate Circuits

10.1. Switching Circuits

10.2. 7400 TTL

10.3. TTL parameters

10.4. TTL Overvew

10.5. Open Collecter Gates

10.6. Three‐state TTL Devices

10.7. External Drive for TTL Lods

10.8. TTL Driving External Loads

10.9. 74C00 CMOS

10.10. CMOS Characteristics

10.11. TTL‐ to –CMOS Interface

10.12. CMOS‐ to‐ TTL Interface

11. Applications

11.1. Multiplexing Displays

11.2. Frequency Counters

11.3. Time Measurement